$TITLE ('ENABLE AND DISABLE ISR FUNCTION CALLS')
$SYMBOLS
$NOXREF
$NOCOND
$NOMOD51
$NORB
$PAGELENGTH(80) PAGEWIDTH(110)
;************************************************************************
;*									*
;*    R T X - 5 1  :  ENABLE AND DISABLE ISR FUNCTION CALLS             *
;*							     		*
;*----------------------------------------------------------------------*
;*                                                                      *
;*    Filename     :   RTXENABL.A51                                     *
;*    Language     :   Keil A-51                                        *
;*    Dev. system  :   Keil uVision2                                    *
;*    Targetsystem :   Any system based upon 8051 up                    *
;*                                                                      *
;*    Purpose      :   Implements the os_enable_isr and the             *
;*                     os_disable_isr function calls.                   *
;*								     	*
;*----------------------------------------------------------------------*
;* Rev. |  Released   | Programmer    | Comments                        *
;*----------------------------------------------------------------------*
;* 0.1  |  29.5.1991  | Th. Fischler  | Module creation                 *
;* 1.0  |  6.12.1991  |               | Enable/Dsable with Fast-Task    *
;*      |             |               | corrected                       *
;* 1.1  |  9.4.1992   |               | Returnvalue corrected           *
;*      | 25.6.1992   |               | Global interrupt disable while  *
;*      |             |               | updating the interrupt mask-    *
;*      |             |               | variables -> for the set/reset  *
;*      |             |               | int_mask functions              *
;* 5.00 | 20.10.1994  | E. Glatz      | Release 5.00                    *
;* 7.00 | 13.11.2001  | T. Mueller    | Release 7.00                    *
;************************************************************************
;*    Copyright 1991 .. 2001 METTLER  &  FUCHS  AG,  CH-8953 Dietikon   *
;************************************************************************


$INCLUDE (RTXDEBUG.INC)
$INCLUDE (RTXIMASK.INC)


;*----------------------------------------------------------------------*
;*	I M P O R T S
;*----------------------------------------------------------------------*

$INCLUDE (RTXCONST.INC)
$INCLUDE (RTXEXTRN.INC)

;*----------------------------------------------------------------------*
;*	E X P O R T S
;*----------------------------------------------------------------------*

PUBLIC  _os_enable_isr
PUBLIC  _os_disable_isr


;*----------------------------------------------------------------------*
;*	P R O C E D U R E S
;*----------------------------------------------------------------------*

;*----------------------------------------------------------------------*
;*      C H E C K _ I N P U T _ P A R A
;*----------------------------------------------------------------------*
;*      Common test-procedure for both function calls
;*----------------------------------------------------------------------*
;*      Input: - R7: interrupt-nbr
;*      -----
;*
;*
;*      Output: - ACC = 0: ALL OK
;*      ------    ACC = 1: ERROR
;*
;*              - R1/R2/R3 holds the interrupt masks
;*----------------------------------------------------------------------*

?RTX?CHECK_INPUT_PARA?RTXENABL     SEGMENT CODE
                                   RSEG ?RTX?CHECK_INPUT_PARA?RTXENABL

CHECK_INPUT_PARA:
               MOV   A, R7
               SETB  C
               SUBB  A, #?RTX_MAX_INT_NBR
               JC    PARA_OK
               ; Input parameter is not ok
               MOV   A, #1
               RET

PARA_OK:       ; Check if the interrupt is used by an ISR
               MOV   DPTR, #?RTX_ISRDESCR
               MOV   A, R7
               MOVC  A, @A+DPTR
               JNZ   USED_BY_ISR
               ; Interrupt is not used by an ISR
               MOV   A, #1
               RET

USED_BY_ISR:   ; Check if the processor supports this interrupt
               MOV   DPTR, #?RTX_INT_TO_BIT_TABLE_BASE
               MOV   A, R7
               MOV   B, #3                      ; 3 Bytes/INT in the table
               MUL   AB
               MOV   R0, A                      ; save the ACC
               ; Load the Interrupt-masks to reg. R1/R2/R3
               MOVC  A, @A+DPTR
               ANL   A, #07FH                   ; to be sure EA-Bit not set
               MOV   R1, A
               INC   R0
               MOV   A, R0
               MOVC  A, @A+DPTR
               MOV   R2, A
               INC   R0
               MOV   A, R0
               MOVC  A, @A+DPTR
               MOV   R3, A
               ; Check the masks
               CLR   A
               ORL   A, R1
               ORL   A, R2
               ORL   A, R3
               JNZ   PROC_OK
               ; processor does not support this interrupt
               MOV   A, #1
               RET
PROC_OK:       MOV   A, #0
               RET


;*----------------------------------------------------------------------*
;*      O S _ E N A B L E _ I S R
;*----------------------------------------------------------------------*
;*      System call for enabling an ISR-interrupt
;*----------------------------------------------------------------------*
;*      Input:  - R7: interrupt number (0..31)
;*      -----
;*
;*      Output: - R7: Function result (OK, NOT_OK)
;*      ------
;*
;*----------------------------------------------------------------------*

?RTX?_os_enable_isr?RTXENABL     SEGMENT CODE
                                 RSEG ?RTX?_os_enable_isr?RTXENABL

_os_enable_isr:
               DBG_SYS_ENTRY
               RTX_EXCLUDE_INT
               SETB  ?RTX_SUPERVISOR_MODE        ; Supervisor_mode := on

               POP   ?RTX_TMP1                   ; Make free 2 Bytes for
               POP   ?RTX_TMP2                   ; subroutine call
               CALL  CHECK_INPUT_PARA
               PUSH  ?RTX_TMP2
               PUSH  ?RTX_TMP1
               JZ    ALL_OK1
               MOV   R7, #NOT_OK
               JMP   END_ENABLE

ALL_OK1:       ; All OK, set the INT-masks
               GLOBAL_INT_DISABLE                ; Do not allow ISR's
               MOV   R7, #OK
               MOV   A, R1
               ORL   A, #80H                     ; To be sure EA-Bit is set
               ORL   ?RTX_NM_IE, A
               ORL   ?RTX_D_IE, A
               ORL   ?RTX_ND_IE, A
               JNB   ?RTX_ENA_INT_REG1, END_ENABLE
               MOV   A, R2
               ORL   ?RTX_NM_IE1, A
               ORL   ?RTX_D_IE1, A
               ORL   ?RTX_ND_IE1, A
               JNB   ?RTX_ENA_INT_REG2, END_ENABLE
               MOV   A, R3
               ORL   ?RTX_NM_IE2, A
               ORL   ?RTX_D_IE2, A
               ORL   ?RTX_ND_IE2, A

END_ENABLE:    RTX_EXCLUDE_INT                   ; Enables the ISR-INT's
                                                 ; and the global INT-Bit
               CLR   ?RTX_SUPERVISOR_MODE        ; supervisor_mode := OFF
               DBG_SYS_EXIT
               RTX_ALLOW_INT
               RET


;*----------------------------------------------------------------------*
;*      O S _ D I S A B L E _ I S R
;*----------------------------------------------------------------------*
;*      System call for disabling an ISR-interrupt
;*----------------------------------------------------------------------*
;*      Input:  - R7: interrupt number (0..31)
;*      -----
;*
;*      Output: - R7: Function result (OK, NOT_OK)
;*      ------
;*
;*----------------------------------------------------------------------*

?RTX?_os_disable_isr?RTXENABL    SEGMENT CODE
                                 RSEG ?RTX?_os_disable_isr?RTXENABL

_os_disable_isr:
               DBG_SYS_ENTRY
               RTX_EXCLUDE_INT
               SETB  ?RTX_SUPERVISOR_MODE        ; Supervisor_mode := on

               POP   ?RTX_TMP1                   ; Make free 2 Bytes for
               POP   ?RTX_TMP2                   ; subroutine call
               CALL  CHECK_INPUT_PARA
               PUSH  ?RTX_TMP2
               PUSH  ?RTX_TMP1
               JZ    ALL_OK2
               MOV   R7, #NOT_OK
               JMP   END_DISABLE

ALL_OK2:       ; All OK, set the INT-masks
               GLOBAL_INT_DISABLE                ; Do not allow ISR's
               MOV   R7, #OK
               MOV   A, R1
               CPL   A
               ORL   A, #80H                     ; To be sure EA-Bit is set
               ANL   ?RTX_NM_IE, A
               ANL   ?RTX_D_IE, A
               ANL   ?RTX_ND_IE, A
               JNB   ?RTX_ENA_INT_REG1, END_DISABLE
               MOV   A, R2
               CPL   A
               ANL   ?RTX_NM_IE1, A
               ANL   ?RTX_D_IE1, A
               ANL   ?RTX_ND_IE1, A
               JNB   ?RTX_ENA_INT_REG2, END_DISABLE
               MOV   A, R3
               CPL   A
               ANL   ?RTX_NM_IE2, A
               ANL   ?RTX_D_IE2, A
               ANL   ?RTX_ND_IE2, A

END_DISABLE:   RTX_EXCLUDE_INT                   ; Disables the ISR-INT
                                                 ; and enables the global
                                                 ; INT-Bit
               CLR   ?RTX_SUPERVISOR_MODE        ; supervisor_mode := OFF
               DBG_SYS_EXIT
               RTX_ALLOW_INT
               RET

;
;   END OF MODULE
;
	END
